A central processing unit (CPU) may access a peripheral device, such as a printer or video card using memory mapped input-output (MMIO). MMIO employs the same address bus to address both physical memory and I/O devices (e.g., physical peripheral devices). Each of the memory as well as registers of I/O devices are mapped to (associated with) memory address values. When an address is accessed by the CPU, the accessed address may refer to a portion of physical RAM, but it can also refer to memory (e.g., registers) of an I/O device in an address space of the I/O device. CPU instructions employed to access the physical memory may also be used for accessing peripheral (I/O) devices as well. Each I/O device monitors the address bus of the CPU and responds to any CPU access of an address assigned to the I/O device, connecting the data bus associated with the CPU to the hardware register of the I/O device. To accommodate I/O devices, blocks of addresses used by the host I/O device may be reserved for I/O and not be available for CPU physical memory.
Virtualization permits multiplexing of an underlying host machine (associated with a physical CPU) between different virtual machines. The host machine or “host” allocates a certain amount of its resources to each of the virtual machines. Each virtual machine may then use the allocated resources to execute applications, including operating systems (referred to as guest operating systems (OS) of a “guest”). The software layer providing the virtualization is commonly referred to as a hypervisor and is also known as a virtual machine monitor (VMM), a kernel-based hypervisor, or a host operating system of the host.
A virtual machine may access a virtual device using guest page addresses corresponding to memory space assigned to the virtual device for purposes of communicating with the virtual device, which is known as memory-mapped input/output (MMIO). The hypervisor may expose a virtual device to the guest to permit the guest to execute instructions on the virtual device. If a virtual device is a virtual peripheral device, such as a virtual printer or virtual video card, the virtual device may be accessed using memory mapped input-output (MMIO).
When a guest address is accessed by the guest, the accessed guest address may refer to a portion of guest RAM or to guest memory of a virtual I/O device. CPU instructions used to access the guest memory may be used for accessing virtual I/O devices. To accommodate virtual I/O devices, blocks of guest addresses used by the virtual devices may be reserved for I/O and not be available for guest physical memory.
During execution of an MMIO-based instruction of the guest, the guest may attempt to access a guest address mapped to a memory space corresponding to the virtual device. The associated CPU typically translates the guest address to a hypervisor address by “walking” through page table entries of a host page table located in the host memory. In the host page table, entries for guest addresses mapped to a memory space of the virtual device are typically marked as invalid, or reserved, to prevent the guest from directly accessing such addresses and, thus, trigger an exit to the hypervisor. Consequently, the results of this relatively computationally-expensive page walk are not stored (“cached”) by the CPU, and the page walk has to be re-executed on each access. On exit to the hypervisor, the hypervisor is usually provided by the CPU with only the guest address that the guest attempted to access. In order for the hypervisor to identify the associated MMIO instruction(s) and associated parameter(s) (e.g., one or more operands), the hypervisor typically executes a lookup in a hypervisor data structure. As all devices in the virtual machine (on which the guest is running) using MMIO should have an entry in the hypervisor data structure, this hypervisor data structure might potentially be very large, and the lookup can be relatively computationally expensive.